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NXP Semiconductors /LPC800 /CRC /MODE

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Interpret as MODE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CRC_POLY 0 (BIT_RVS_WR)BIT_RVS_WR 0 (CMPL_WR)CMPL_WR 0 (BIT_RVS_SUM)BIT_RVS_SUM 0 (CMPL_SUM)CMPL_SUM 0Reserved

Description

CRC mode register

Fields

CRC_POLY

CRC polynom: 1X= CRC-32 polynomial 01= CRC-16 polynomial 00= CRC-CCITT polynomial
BIT_RVS_WR

Data bit order: 1= Bit order reverse for CRC_WR_DATA (per byte) 0= No bit order reverse for CRC_WR_DATA (per byte)
CMPL_WR

Data complement: 1= 1’s complement for CRC_WR_DATA 0= No 1’s complement for CRC_WR_DATA
BIT_RVS_SUM

CRC sum bit order: 1= Bit order reverse for CRC_SUM 0= No bit order reverse for CRC_SUM
CMPL_SUM

CRC sum complement: 1= 1’s complement for CRC_SUM 0=No 1’s complement for CRC_SUM
Reserved

Always 0 when read

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data